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Chapter 1: About the FIR Compiler
Device Family Support
Device Family Support
Table 1–3 defines the device support levels for Altera IP cores.
Table 1–3. Altera IP Core Device Support Levels
1–5
FPGA Device Families
Preliminary support —The IP core is verified with
preliminary timing models for this device family. The IPcore
meets all functional requirements, but might still be
undergoing timing analysis for the device family. It can be
used in production designs with caution.
Final support —The IP core is verified with final timing
models for this device family. The IP core meets all
functional and timing requirements for the device family and
can be used in production designs.
HardCopy Device Families
HardCopy Companion —The IP core is verified with
preliminary timing models for the HardCopy companion
device. The IP core meets all functional requirements, but
might still be undergoing timing analysis for the HardCopy
device family. It can be used in production designs with
caution.
HardCopy Compilation —The IP core is verified with final
timing models for the HardCopy device family. The IP core
meets all functional and timing requirements for the device
family and can be used in production designs.
Table 1–4 shows the level of support offered by the FIR Compiler to each Altera
device family.
Table 1–4. Device Family Support
Arria ? GX
Arria II GX
Arria II GZ
Cyclone ?
Cyclone II
Cyclone III
Cyclone III LS
Cyclone IV GX
HardCopy ? II
HardCopy III
HardCopy IV E
HardCopy IV GX
Device Family
Support
Final
Final
Final
Final
Final
Final
Final
Final
HardCopy Compilation
HardCopy Compilation
HardCopy Compilation
HardCopy Compilation
Stratix
?
Final
Stratix II
Stratix II GX
Stratix III
Stratix IV GT
Stratix IV GX/E
Stratix V
Stratix GX
Other device families
Final
Final
Final
Final
Final
Preliminary
Final
No support
? May 2011
Altera Corporation
FIR Compiler User Guide
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